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Category:Defunct Ontario provincial electoral districtsThe present invention relates generally to the field of delay lines, and more particularly to delay line circuitry for use in high speed communications systems.
Delay lines are commonly used in high speed communication systems as part of a clock recovery apparatus for performing clock recovery tasks in digital communication systems. In most high speed communication systems, a significant number of high speed symbols are transmitted for each symbol period. Such high speed communication systems require circuitry with a high bandwidth to properly receive and process the high speed symbols. Typically, the majority of the circuitry in high speed communication systems includes delay line circuitry to generate a clock that is substantially the same as the symbol frequency. Such circuitry is usually coupled to a data processing apparatus such as a receiver, a decoder, or the like.
Conventionally, delay line circuitry is made up of a plurality of delay line buffers connected in series. Each delay line buffer is made up of an input buffer circuit, which receives the input signal, and an output buffer circuit, which receives the output signal from the input buffer circuit, and generates the delayed output signal. Typically, when the output signal is provided at a low level, the output buffer circuit in each delay line buffer is enabled so that the output signal is provided at the low level, while the output signal is provided at a high level when the output signal is provided at a high level
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